The invention relates to a semiconductor device comprising a semiconductor body including a substrate and a stack of a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region having a second doping concentration, which is lower than the first doping concentration, a third semiconductor region of a second, opposite conductivity type having a third doping concentration ranging between the first and the second doping concentration, a fourth semiconductor region of the first conductivity type having a fourth doping concentration, which is higher than the third doping concentration, the first and the fourth semiconductor regions being provided with an electrical connection conductor, one of which is situated on the side of the substrate and the other is situated at the surface of the semiconductor body, an electric voltage being applied across said connection conductors during operation of the device, the thickness and the doping concentration of the second and the third semiconductor region being chosen to be such that they are completely depleted during operation. Such a device, which is also referred to as punch-through diode, is an attractive alternative to Zener diodes, particularly for operating voltages below approximately 5 volts, to suppress peak voltages, which can be attributed to the fact that such a device exhibits a steep punch-through characteristic and a low capacitance.
Such a device is disclosed in U.S. Pat. No. 5,880,511, published Mar. 9, 1999. In said document, a description is given of a diode with an n++ substrate supporting a stack of regions, respectively a pxe2x88x92, a p+ and an n++ region. The substrate and the uppermost n+ region are provided with connection conductors. The diode is mesa-shaped and the flanks are covered with an electrically insulating layer.
Experiments have shown that a drawback of the known device resides in that the I-V (=current-voltage) characteristic of the diode does not exhibit the desired trend, i.e. it does not exhibit a straight and steep transition, particularly when the known device is designed such that the so-called punch-through voltage is above 2 volts. In addition, the diode behavior is not stable.
Therefore, it is an object of the invention to provide a device of the type mentioned in the opening paragraph, wherein said drawback is overcome or at least substantially reduced, and which device exhibits a very straight and steep I-V, also if the punch-through voltage is above 2 volts, and which device is very stable.
To achieve this, a device of the type mentioned in the opening paragraph is characterized in accordance with the invention in that the first semiconductor region adjoins the surface of the semiconductor body, and the fourth semiconductor region is situated on the side of the substrate. It has been found that such a device exhibits a very steep I-V characteristic, also in the case of a design voltage (?) above 2 volts. The invention is based on the following recognition. A punch-through diode can be regarded as a bipolar transistor having an open base, i.e. without a base terminal. When the device is subjected to a forward voltage, the junction between the (lightly doped) pxe2x88x92 region and the n++ region, or if instead of a lightly doped pxe2x88x92 region, a lightly doped nxe2x88x92 region is present between the p+ and the nxe2x88x92 region, is slightly forward biased. This means that the n++ region then serves as the emitter of the transistor, the p+ region serves as the base and the pxe2x88x92 region as a part of the base, and the n++ substrate forms the collector. If the collector-emitter breakdown voltage of the transistor (=BVCEO) is lower than the punch-through voltage at any current intensity, the diode will exhibit a negative resistance behavior. This may cause instability, such as undesirable oscillation. A relation between the BVCEO and the junction breakdown voltage (=BVCBO) is: BVCEO=BVCBO/xcex2l/n, wherein xcex2 is the current amplification, which is equal to the quotient of the base current (ib) and the collector current (ic), and n has a value between 3 and 4. The base current is determined by the recombination of holes and electrons in the lightly doped region, i.e. the pxe2x88x92 or the nxe2x88x92 region. In the known diode, the current amplification may be very high since the recombination in said regions is very low due to the long recombination lifetime of charge carriers in (bulk) silicon. This is the reason why BVCEO is low. If the first conductivity type is the nxe2x88x92 conductivity type, then, in a structure inverted in accordance with the invention, the n++ top region is required only to make satisfactory contact with the connection conductor. Said top region does serve as a barrier for holes but it can be embodied so as to be very thin. This means that many holes can recombine at the interface between the silicon and the connection conductor. Simulations have shown that, as a result thereof, the current amplification can be reduced by as much as a factor of 10. This serves as an explanation for the above-mentioned excellent results.
In an important embodiment, the first conductivity type is the n-conductivity type, and the second semiconductor region is of the second conductivity type, i.e. the p-conductivity type. Choosing the n-conductivity type has the advantage that the punch-through current is carried by electrons which, owing to their higher mobility, yield a lower series resistance, leading to limited power losses. Although the second semiconductor region may also be a lightly doped n-region, a second semiconductor region which is lightly p-doped results in a slightly higher base current and hence a slightly lower xcex2, which, on account of the above, is favorable.
In a favorable modification, parts of at least the second and the third semiconductor region adjoin the surface of the semiconductor body, for example in that they form part of a mesa, and are covered with an electrically insulating layer over which one of the connection conductors extends. An important additional advantage of a device in accordance with the invention is that, in this modification, the uppermost connection conductor, provided it overlaps the p+ region at the edges, can serve as a field plate. This implies that in the case of a positive voltage on the n++ region adjoining the p+ region, i.e. at a forward voltage, premature punch-through at the edge of the mesa is precluded. This too results in an increased steepness of the I-V characteristic, which is desirable. In the known device, on the contrary, such a field plate would lead to premature punch-through and hence enhance a non-steep I-V characteristic.
In a particularly favorable further modification, wherein the semiconductor body comprises silicon, the first semiconductor region comprises a mixed crystal of silicon and germanium.
By virtue of the presence of this mixed crystal, the above-mentioned barrier is further reduced. As a result, the current amplification can be further reduced, even a reduction by a factor of the order of one hundred being possible.
Also a small thickness of the first semiconductor region, for example in the range between 10 and 100 nm, contributes to a limited barrier-effect of this region. Such small thicknesses also enable the use of a silicon-germanium mixed crystal comprising a substantial germanium content, for example a content in the range from 20 to 30 atom %.
A method of manufacturing a semiconductor device, wherein a semiconductor body with a substrate is formed, which semiconductor body is provided with a stack of a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region having a second doping concentration, which is lower than the first doping concentration, a third semiconductor region of a second, opposite conductivity type having a third doping concentration ranging between the first and the second doping concentration, and a fourth semiconductor region of the first conductivity type having a fourth doping concentration, which is higher than the third doping concentration, the first and the fourth semiconductor region being provided with an electric connection conductor across which an electric voltage is applied during operation of the device, and the thickness and the doping concentration of the second semiconductor region being chosen to be such that, during operation, the second semiconductor region is completely depleted, is characterized in accordance with the invention in that the first semiconductor region is positioned at the surface of the semiconductor body, and the fourth semiconductor region is positioned on the side of the substrate. Such a method enables a device in accordance with the invention to be obtained in a simple manner.
Preferably, the n-type is chosen as the first conductivity type, and the second semiconductor region is provided with the p-conductivity type. In a favorable modification, parts of at least the second and the third semiconductor region adjoining the surface of the semiconductor body are provided with an electrically insulating layer, and one of the connection conductors is formed such that it extends over the insulating layer. In a favorable modification, the first semiconductor region is made of a mixed crystal of silicon and germanium. This region preferably has a thickness in the range between 10 and 100 nm.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.